fujitsu semiconductor data sheet copyright?2012 fujitsu semiconductor limited all rights reserved 2012.6 semicustom cmos standard cell CS402 series description the CS402 series of 28 nm standard cells is a line of cmos asics of high-performance with minimum power consumption. by the adoption of core transistors with high current drivability operating at low voltages, the operating frequency approximately twice that of cs401 series is realized at power supply voltages 10% lower than those of cs401 series. this series is appropriate for high-performance/high- end applications ranging from the engines of handheld terminals to telecommunication equipment. features ? technology : 28 nm metal-gate cmos : maximum 11-metal layers. ultra low permittivity material is used for inter-layer dielectric. : core transistors with different thres hold voltages can be used on the same chip (ultra low leak, low leak, standar d, high speed and ultra high speed). ? supply voltage : internal power supply : + 0.9 v 0.09 v : external power supply : + 1.8 v 0.15 v (1.8v interface on dual-power supply system) ? junction temperature range: ? 40 c to + 125 c (standard specification) ? operating frequency: approximately twice that of cs401 series ? support various types of high-quality cell sets de veloped by fujitsu semiconductor (from low power versions to high speed versions). ? support srams with standby-mode and power-dow n mode for lower power consumption memories. ? compiled cells (ram, rom, others) ? support special interfaces (lvds, sstl, others). ? support boundary scan test. ? support use of industry standard libraries. ? support use of industry standard tools. ? short-term development using a physical prototyping tool ? one-pass design using a physical synthesis tool ? hierarchical design environment for supporting large-scale circuits ? support signal integrity, emi noise reduction. ? support static timing sign-off. ? improve timing convergence by the introduction of statistical static timing analysis (ssta). ? design for manufacturing (dfm) enables stab le product-supply and reduced variation. ? package lineup: fbga, pbga, tebga, fc-bga note: including items under development. ds601-00002-0v01-e
CS402 series 2 ds601-00002-0v01-e macro libraries (macros currently being prepared are included) 1. logic cells (about 400 types) library sets for four types of core transistors with different threshold voltages. ? adder ? and ? and-or ?and-or inverter ? buffer ? clock-buffer ? delay buffer ? enor ? eor ?inverter ? latch ? nand ?nor ? or ? or-and ? or-and inverter ? scan flip flop ? non-scan flip flop ? selector ? others 2. ip macros *: arm, arm7tdmi-s, arm946e-s, arm926ej-s, arm1176jzf-s, cortex-m3, cortex-r4f and cortex-a9 are the trademarks of arm limited in the eu and other countries. 3. special i/o interface macros cpu/dsp arm tm * cores (arm7tdmi-s tm *, arm946e-s tm *, arm926ej-s tm *, arm1176jzf-s tm *, cortex-m3 tm *, cortex-r4f tm *, cortex-a9 tm * mpcore), peripherals ip mixed signal macro adc, dac,opamp, others compiled macro sram (1 port, 2 port), rom, product sum calculator, others pll analog pll special i/o lvcmos, lvds, sstl
CS402 series ds601-00002-0v01-e 3 compiled cells compiled cells are macro cells that can be automatically generated by specifying the bit/word configuration. the following compiled cells are available for the CS402 series. ? memory capacity name category memory capacity (bit) clock synchronous single-port ram (1rw) high-density 64 to 1152k high-speed 32 to 80k large-scale tbd clock synchronous dual port ra m (2rw) high-density 32 to 144k clock synchronous rom ? 128 to 1152k clock synchronous register file (1rw) high-speed 96 to 36k high-density 96 to 36k clock synchronous register file (1r1w) high-speed 32 to 36k high-density 128 to 72k clock synchronous register file (2r2w) ? 16 to 18k
CS402 series 4 ds601-00002-0v01-e absolute maximum ratings *1: v ss = 0 v *2: internal gates *3: 1.8 v interface on dual-power supply system *4: the output current varies depending on the number of chip metal layers and the wiring configuration of the i/o cells. for details, contact the sales representative. *5: for details about the power supply pin cu rrent, contact the sales representative. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 v dd ? 0.4 + 1.3 v *2 ? 0.5 + 2.5 *3 input voltage* 1 vi ? 0.5 v dd + 0.5 ( 2.5 v ) v *3 output voltage* 1 vo ? 0.5 v dd + 0.5 ( 2.5 v ) v *3 storage temperature t stg ? 55 + 125 c junction temperature tj ? 40 + 125 c output current* 4 io ?? ma power supply pin current* 5 id ?? ma
CS402 series ds601-00002-0v01-e 5 design methods fujitsu semiconductor's reference design flow provides the following functions that help reduce the devel- opment time of large scale, high quality lsis. ? statistical static timing analysis (ssta) improves timing convergence. ? physical prototyping enables more accurate estimation of highly reliable designs. ? layout synthesis with optimized timing is realized by physical synthesis tool. ? high accuracy design environment where voltage dr op of power supply, signal noise, delay penalty and crosstalk are considered ? i/o design environment (power line design, assignme nt and selection of i/os, package selection) where noise is considered packages the CS402 series can use the same packages that are available for th e previous series, allowing a smooth transition from previously developed models. for details of delivery times, contact the sales representative. ? fbga packages ? pbga packages ? tebga packages ? fc-bga packages
CS402 series 6 ds601-00002-0v01-e memo
CS402 series ds601-00002-0v01-e 7 memo
CS402 series fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 902 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ fujitsu semiconductor shanghai co., ltd. 30f, kerry parkside, 1155 fang dian road, pudong district, shanghai 201204, china tel : +86-21-6146-3688 fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such informa tion. when you develop equipment incorporat ing the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent ri ght or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-part y's intellectual property right or other ri ght by using such information. fujitsu semiconductor assumes no liab ility for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any thir d party for any claims or damages aris- ing in connection with above-mentioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department
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